Core Test Engineering
Ardentec’s core test engineering capability is on wafer probing. Solid test engineering knowledge allows our team to provide yield analysis and enhancement suggestions to customers in logic, mixed-signal, analog, RF, memory, and LCD driven IC devices.
Empyrean AetherTM (Schematic and Layout Design Platform)
Empyrean Aether delivers a complete, integrated solution for custom IC designs using OpenAccess™ as the native database. This platform has several built-in modules such as design manager (Aether-DM), technology manager (Aether-TM), schematic editor (Aether-SE), layout editor (Aether-LE), schematic-driven layout (Aether-SDL), mixed-signal simulation environment (Aether-MDE), etc.
Empyrean-XTop is a genuine placement- and routing-aware, multi-corner, multi-mode timing ECO solution with minimal impact to power and area in nanometer-scale IC designs.
Timing closure is a major problem with today’s SOC designs impacting time to market, revenue, and cost of design. It gets worse with each new process node. Empyrean-XTop helps design teams to achieve faster timing /ECO closure and complements existing place and route and sign-off static timing analysis STA (Static Timing Analysis) tools in a user’s flow.
Empyrean-XTop has been used in production for over a decade. It provides much faster timing closure convergence than conventional timing ECO flows.
Heavy Duty Shelving Pallet Rack for Warehouse Storage
Ardentec is a professional testing company providing semiconductor wafer and IC test related services.